Job Description
Foundry Technology and Engineering (FTE) team is chartered with technology and production enablement of Intel products with our 3rd party Foundry and internal/external assembly and test suppliers as per Intel IDM2.0 Vision. DTQ (Design for Test and Quality) team is chartered to drive design and dft changes and improvements for better circuit marginality and product quality and lower test cost. DTQ team seeks Staff Implementation engineers to support its operations. A unique opportunity of dealing with the most advanced STCO/DTCO techniques, cutting-edge design and technology processes and interacting with the respective stakeholders within the whole company and suppliers’ eco-system from early phase to production ramp and pursue flawless design qualities.
Job responsibilities include:
Engage with multiple SOC/IP design teams starting from architecture definition phase and drive leading aggregated power, performance, timing and margin requirements in single die and/or multi-die environment.
Define, monitor and review products implementation/signoff quality metrics from early design/technology phase (pre-TO) to yield driven (post silicon / NPI) validating timing figures, signal integrity and IR drop margins.
Lead in reducing design marginalities and enlarging process windows.
Lead in developing state-of-the-art methodologies for correlating silicon readings with design timing margins using as-is or new EDA ecosystems (drive EDA partners).
A successful candidate must demonstrate:
Excellent scripting skills to automate flows/design debug frameworks.
Experience with SOC implementation tools, flows and processes, power/IR aware STA flows.
Experience with static timing, signal integrity and power analysis across PVT.
Experience with 3DIC implementation flows and timing signoff methodologies.
Experience with circuit / critical paths spice level analysis/statistical simulations.
Experience with synthesis and STA constraints generation and verification tools and flows.
Experience with synthesis, formal verification and ECO tools and flows.
Familiarity with SOC architecture, tile/chiplet based integration, clock and power architectures.
Familiarity with library modeling and characterization.
Familiarity with DFT/design architectural concepts
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. This position is not eligible for Intel Immigration sponsorship.
Minimum Qualifications:
BS in STEM or related field
5+ years of physical design engineering experience or related or MS with 4+ years of physical design engineering experience or related, PhD with 2+ years of physical design engineering experience or related.
Inside this Business Group
Intel’s Sales and Marketing (SMG) organization works with global customers and partners to solve critical business problems with Intel based technology solutions. SMG works across business units to amplify the customer voice and deliver solutions that accelerate their business. We work across numerous industries, including retail, enterprise and government, cloud services and healthcare as examples. The operations team focuses on forecasting, driving alignment with factory production and delivering efficiency tools and our marketing capability drives demand and localized marketing in locations around the globe. Our sales force navigates a complex partner and customer ecosystem while shaping product roadmaps, driving value for our customers, and collaborating to harness emerging technology trends to deliver comprehensive solutions.
Other Locations
US, OR, Hillsboro; US, AZ, Phoenix
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://jobs.intel.com/en/benefits
Annual Salary Range for jobs which could be performed in US, California: $118,860.00-$196,720.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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